Classes | |
| struct | Instance |
Typedefs | |
| using | Rung = signal::Rungler |
Functions | |
| float | rungler_worst_case_gain () |
| Worst-case linear gain for the Forge registry (series law 8). | |
| float | rungler_output_bound_v () |
| The largest absolute output the node can emit, in volts: the ceiling of the range_v param, because a baked param can be automated anywhere in range. | |
| CustomNodeType | make_rungler_node (int reg_bits=Rung::kDefaultBits, std::uint32_t seed_pattern=Rung::kSeedPattern) |
| reg_bits and seed_pattern are registration-time. | |
| ForgeNodeDescriptor | descriptor () |
Variables | |
| constexpr const char * | kTypeId = "sequencing.rungler" |
| constexpr state::ParamID | kRun = 1 |
| constexpr state::ParamID | kDacBits = 2 |
| constexpr state::ParamID | kFeedbackTap = 3 |
| constexpr state::ParamID | kRangeV = 4 |
| constexpr state::ParamID | kExternalData = 5 |
| constexpr state::ParamID | kDataIn = 6 |
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inline |
| CustomNodeType pulp::host::sequencing::rungler::make_rungler_node | ( | int | reg_bits = Rung::kDefaultBits, |
| std::uint32_t | seed_pattern = Rung::kSeedPattern ) |
reg_bits and seed_pattern are registration-time.
seed_pattern because a seed is which performance you are playing (law 2). reg_bits because the DSP reloads the seed when the register length changes — a register whose length moves mid-orbit has no meaningful "same state" — so as an injectable param it would re-pin the sequence on every sample and the node would emit one frozen level instead of a line.
| float pulp::host::sequencing::rungler::rungler_output_bound_v | ( | ) |
The largest absolute output the node can emit, in volts: the ceiling of the range_v param, because a baked param can be automated anywhere in range.
| float pulp::host::sequencing::rungler::rungler_worst_case_gain | ( | ) |
Worst-case linear gain for the Forge registry (series law 8).
This is the one block in the module with a feedback path, so law 8 bites here — and the answer is a PROVEN bound rather than a measurement. The feedback is a single-bit XOR into a shift register: there is no gain-carrying analog nonlinearity, so no small-signal-gain compensation applies. The output is a D-bit DAC code mapped affinely onto [−range_v, +range_v], so |y| ≤ range_v BY CONSTRUCTION for any clock or data sequence whatsoever. The DSP suite asserts exactly that over 10⁶ clocks of adversarial data (all-ones, alternating, xorshift) at three configurations, and asserts the bound is TIGHT — both extremes are reached. Reported as 1.0 because there is no input-to-output amplitude path at all; the absolute output bound is range_v, whose param ceiling is below.
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